The BSD SD subsystem enforces a 50MHz clock cap for devices which don't
report their own maximum clock speed. This setting is unnecessary for
the Zynq 7000 version of this IP and restricts the Zynq Ultrascale+
MPSoC version of this IP without need since it reports its maximum speed
as 200MHz.
The initial version of this driver was masking the capabilities register
to hide 8 bit bus capability. This is not necessary since these devices
report that capability correctly and the masking affects performance
negatively on ZynqMP boards where the 8 bit bus is supported. This also
removes two quirks that were made necessary by the capabilities masking.
Probing a SDIO/SDHCI interface that has been disabled by system init via
holding it in reset can cause a CPU hang. This prevents probing of
devices that have been disabled in such a manner on ZynqMP systems.
