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1,932 Commits 6 Branches 8 Tags
Commit Graph

13 Commits

Author SHA1 Message Date
Kinsey Moore
e256668d6e nexus: Add ZynqMP SLCR driver 
Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
 2021-03-10 08:57:59 -06:00
Kinsey Moore
68e79b6d18 zynq: Add support for SDHCI devices 2020-12-22 16:12:58 -06:00
Kinsey Moore
0ad342ae5f Add CGEM definitions for ZynqMP 2020-11-24 08:50:07 -06:00
Sebastian Huber
c30fa94277 Add device tree support for Altera/Intel Cyclone V 
Close #3290.
 2018-02-06 09:55:31 +01:00
Christian Mauderer
ec29b2a0c2 at91_mci: Port to RTEMS and adapt for atsam. 2017-11-10 14:13:15 +01:00
Christian Mauderer
589220752b saf1761_otg: Port to RTEMS. 2017-11-10 14:01:55 +01:00
Christian Mauderer
80a7fe68a1 if-atsam: Port to rtems-libbsd. 2017-09-22 10:17:24 +02:00
Kevin Kirspel
e28a8d01c1 Add LPC32XX touch screen driver 2017-05-19 07:24:30 +02:00
Sebastian Huber
ae9e46d7c5 Fix dw_mmc dependencies 2017-03-01 10:49:05 +01:00
Kevin Kirspel
9f2205a3f5 Port LPC32XX Ethernet and USB OHCI to RTEMS 2017-02-14 09:40:01 +01:00
Sebastian Huber
c40e45b75e Update to FreeBSD head 2016-08-23 
Git mirror commit 9fe7c416e6abb28b1398fd3e5687099846800cfd.
 2017-01-10 09:53:31 +01:00
Chris Johns
f588325390 Change the Nexus bus to defines and have the BSP declare them. 2016-06-28 13:30:44 +10:00
Chris Johns
459d67d537 Move the Nexus bus driver decls available to users. 2016-06-27 13:35:08 +10:00