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2 Commits

Author SHA1 Message Date
Chris Johns
25a883272a Add support for Xilinx Versal APAC 2021-10-21 11:29:14 +11:00
Kinsey Moore
e256668d6e nexus: Add ZynqMP SLCR driver 
Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
 2021-03-10 08:57:59 -06:00