mirror of
https://git.rtems.org/rtems-libbsd/
synced 2025-05-14 00:10:02 +08:00

Add a System Level Control Register driver for the Xilinx Zynq Ultrascale+ MPSoC with basic clock control functionality for use with the Cadence GEM. This also removes the Zynq-7000 clock control weakref from compilation depending on the BSP in use.