Kinsey Moore e256668d6e nexus: Add ZynqMP SLCR driver
Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
2021-03-10 08:57:59 -06:00
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2020-12-22 16:12:58 -06:00