mirror of
https://git.rtems.org/rtems-libbsd/
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e256668d6e
Add a System Level Control Register driver for the Xilinx Zynq Ultrascale+ MPSoC with basic clock control functionality for use with the Cadence GEM. This also removes the Zynq-7000 clock control weakref from compilation depending on the BSP in use.
91 lines
3.8 KiB
C
91 lines
3.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Kinsey Moore
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Defines for Zynq Ultrascale+ MPSoC SLCR registers.
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*
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* Reference: Zynq Ultrascale+ MPSoC Technical Reference Manual.
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* (v2.2) December 4, 2020. Xilinx doc UG1085.
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*
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* Additional Reference: Zynq Ultrascale+ MPSoC Register Reference.
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* (v1.7) February 8, 2019. Xilinx doc UG1087.
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*/
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#ifndef _ZYNQMP_SLCR_H_
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#define _ZYNQMP_SLCR_H_
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#define ZYNQMP_SLCR_CRF_OFFSET 0x0d1a0000
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#define ZYNQMP_SLCR_CRL_OFFSET 0x0f5e0000
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/* PLL controls. */
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#define ZYNQMP_SLCR_IO_PLL_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x20)
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#define ZYNQMP_SLCR_R_PLL_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x30)
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#define ZYNQMP_SLCR_D_PLL_CTRL (ZYNQMP_SLCR_CRF_OFFSET + 0x2c)
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#define ZYNQMP_SLCR_PLL_CTRL_RESET (1<<0)
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#define ZYNQMP_SLCR_PLL_CTRL_BYPASS (1<<3)
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#define ZYNQMP_SLCR_PLL_CTRL_FBDIV_SHIFT 8
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#define ZYNQMP_SLCR_PLL_CTRL_FBDIV_MASK (0x7f<<8)
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#define ZYNQMP_SLCR_PLL_CTRL_FBDIV_MAX 0x7f
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#define ZYNQMP_SLCR_PLL_CTRL_DIV2 (1<<16)
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#define ZYNQMP_SLCR_PLL_CTRL_PRE_SRC_SHIFT 20
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#define ZYNQMP_SLCR_PLL_CTRL_PRE_SRC_MASK (0x7<<20)
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#define ZYNQMP_SLCR_PLL_CTRL_POST_SRC_SHIFT 24
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#define ZYNQMP_SLCR_PLL_CTRL_POST_SRC_MASK (0x7<<24)
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_PS 0x0
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_VIDEO 0x4
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_ALT 0x5
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_AUX 0x6
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_GT 0x7
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/* Clock controls. */
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#define ZYNQMP_SLCR_GEM0_CLK_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x50)
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#define ZYNQMP_SLCR_GEM1_CLK_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x54)
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#define ZYNQMP_SLCR_GEM2_CLK_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x58)
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#define ZYNQMP_SLCR_GEM3_CLK_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x5c)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_RX_CLKACT (1<<26)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_CLKACT (1<<25)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_MASK (0x3f<<16)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT 16
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX 0x3f
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR0_MASK (0x3f<<8)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR0_SHIFT 8
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR0_MAX 0x3f
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_SRCSEL_MASK (7<<0)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL (0<<0)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_SRCSEL_R_PLL (2<<0)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_SRCSEL_D_PLL (3<<0)
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#define ZYNQMP_DEFAULT_PS_CLK_FREQUENCY 33333333
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#ifdef _KERNEL
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extern int cgem_set_ref_clk(int unit, int frequency);
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#endif
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#endif /* _ZYNQMP_SLCR_H_ */
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