rtems/rtems-tools
1
0
Fork 0
mirror of https://git.rtems.org/rtems-tools/ synced 2025-10-16 04:10:03 +08:00
Code Issues Packages Projects Releases Wiki Activity

Add cpu registers to task output.

Browse Source
This commit is contained in:
Dhananjay Balan
2013-08-26 22:12:25 +05:30
committed by Chris Johns
parent 5a4834c641
commit bd0b98d55e
2 changed files with 94 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
tools/gdb/python/classic.py
View File

@@ -16,6 +16,7 @@ import threads
import watchdog import watchdog
import heaps import heaps
import supercore import supercore
import sparc
class attribute: class attribute:
"""The Classic API attribute.""" """The Classic API attribute."""
@@ -155,6 +156,8 @@ class task:
self.task = \ self.task = \
threads.control(self.object) threads.control(self.object)
self.wait_info = self.task.wait_info() self.wait_info = self.task.wait_info()
# ToDo: Insert platform dep. code here.
self.regs = sparc.register(self.object['Registers'])
def show(self, from_tty): def show(self, from_tty):
print ' Name:', self.task.name() print ' Name:', self.task.name()
@@ -163,6 +166,8 @@ class task:
print ' Real:', self.task.real_priority() print ' Real:', self.task.real_priority()
print ' Preempt:', self.task.preemptible() print ' Preempt:', self.task.preemptible()
print ' T Budget:', self.task.cpu_time_budget() print ' T Budget:', self.task.cpu_time_budget()
print ' Regsters:'
self.regs.show()
class message_queue: class message_queue:

151
tools/gdb/python/sparc.py
View File

@@ -4,73 +4,75 @@
from helper import test_bit from helper import test_bit
class psr:
'''status register'''
sv_table = {
0 : 'user',
1 : 'superviser'
}
def __init__(self, psr):
self.psr = psr
def current_window(self):
return int(self.psr & 0xf)
def traps(self):
return test_bit(self.psr, 5)
def prev_superviser(self):
return int(test_bit(self.psr,6))
def superviser(self):
return int(test_bit(self.psr,7))
def interrupt_level(self):
# bits 8 to 11
return (self.spr & 0x780) >> 7
def floating_point_status(self):
return test_bit(self.psr, 12)
def coproc_status(self):
return test_bit(self.psr,13)
def carry(self):
return test_bit(self.psr, 20)
def overflow(self):
return test_bit(self.psr, 21)
def zero(self):
return test_bit(self.psr, 22)
def icc(self):
n = test_bit(self.psr,23)
z = test_bit(self.psr,22)
v = test_bit(self.psr,21)
c = test_bit(self.psr,20)
return (n,z,v,c)
def to_string(self):
val = " Status Register"
val += "\n R Window : " + str(self.current_window())
val += "\n Traps Enabled : " + str(self.traps())
val += "\n Flaoting Point : " + str(self.floating_point_status())
val += "\n Coprocessor : " + str(self.coproc_status())
val += "\n Processor Mode : " + self.sv_table[self.superviser()]
val += "\n Prev. Mode : " + self.sv_table[self.superviser()]
val += "\n Carry : " + str(int(self.carry()))
val += "\n Overflow : " + str(int(self.overflow()))
val += "\n Zero : " + str(int(self.zero()))
return val
class register: class register:
'''SPARC Registers''' '''SPARC Registers'''
class psr:
'''status register'''
sv_table = {
0 : 'user',
1 : 'superviser'
}
def __init__(self, psr):
self.psr = psr
def current_window(self):
return int(self.psr & 0xf)
def traps(self):
return test_bit(self.psr, 5)
def prev_superviser(self):
return int(test_bit(self.psr,6))
def superviser(self):
return int(test_bit(self.psr,7))
def interrupt_level(self):
# bits 8 to 11
return (self.spr & 0x780) >> 7
def floating_point_status(self):
return test_bit(self.psr, 12)
def coproc_status(self):
return test_bit(self.psr,13)
def carry(self):
return test_bit(self.psr, 20)
def overflow(self):
return test_bit(self.psr, 21)
def zero(self):
return test_bit(self.psr, 22)
def icc(self):
n = test_bit(self.psr,23)
z = test_bit(self.psr,22)
v = test_bit(self.psr,21)
c = test_bit(self.psr,20)
return (n,z,v,c)
def to_string(self):
val = " Status Register"
val += "\n R Window : " + str(self.current_window())
val += "\n Traps Enabled : " + str(self.traps())
val += "\n Flaoting Point : " + str(self.floating_point_status())
val += "\n Coprocessor : " + str(self.coproc_status())
val += "\n Processor Mode : " + self.sv_table[self.superviser()]
val += "\n Prev. Mode : " + self.sv_table[self.superviser()]
val += "\n Carry : " + str(int(self.carry()))
val += "\n Overflow : " + str(int(self.overflow()))
val += "\n Zero : " + str(int(self.zero()))
return val
def __init__(self,reg): def __init__(self,reg):
self.reg = reg self.reg = reg
@@ -108,8 +110,33 @@ class register:
val.append(self.reg['o'+str(i)]) val.append(self.reg['o'+str(i)])
return val return val
def status(self):
return self.psr(self.reg['psr'])
def show(self):
print ' Global Regs:',
print ' [',
for i in self.global_regs():
print str(i)+',',
print '\b\b ]'
print ' Local Regs:',
print ' [',
for i in self.local_regs():
print str(i)+',',
print '\b\b ]'
print ' In Regs:',
print ' [',
for i in self.in_regs():
print str(i)+',',
print '\b\b ]'
print ' Out Regs:',
print ' [',
for i in self.out_regs():
print str(i)+',',
print '\b\b ]'
sr = self.status()
print sr.to_string()