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https://github.com/riscv-software-src/riscv-isa-sim.git
synced 2025-10-14 02:07:30 +08:00
Remove extra semicolons (-Wpedantic)
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@@ -1231,7 +1231,7 @@ hideleg_csr_t::hideleg_csr_t(processor_t* const proc, const reg_t addr, csr_t_p
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reg_t hideleg_csr_t::read() const noexcept {
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return masked_csr_t::read() & mideleg->read();
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};
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}
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hgatp_csr_t::hgatp_csr_t(processor_t* const proc, const reg_t addr):
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basic_csr_t(proc, addr, 0) {
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@@ -675,4 +675,4 @@ reg_t module_t::tinfo_read(unsigned UNUSED index) const noexcept
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(CSR_TINFO_VERSION_1 << CSR_TINFO_VERSION_OFFSET);
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}
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};
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}
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@@ -301,6 +301,6 @@ private:
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std::vector<trigger_t *> triggers;
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};
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};
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}
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#endif
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@@ -72,13 +72,13 @@ float ## bits ## _t f ## bits ## _min( float ## bits ## _t a, float ## bits ## _
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} \
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}
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COMPARE_MAX(a, b, 16);
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COMPARE_MAX(a, b, 32);
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COMPARE_MAX(a, b, 64);
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COMPARE_MAX(a, b, 16)
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COMPARE_MAX(a, b, 32)
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COMPARE_MAX(a, b, 64)
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COMPARE_MIN(a, b, 16);
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COMPARE_MIN(a, b, 32);
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COMPARE_MIN(a, b, 64);
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COMPARE_MIN(a, b, 16)
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COMPARE_MIN(a, b, 32)
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COMPARE_MIN(a, b, 64)
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bfloat16_t bf16_max( bfloat16_t a, bfloat16_t b )
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{
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