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148 Commits

Author SHA1 Message Date
Andrew Waterman
9145cdcae2 Merge pull request #2094 from chihminchao/enhance-amo-disasm 
disasm: show the acquire and release attribute to amo instructions
 2025-10-01 15:32:33 -07:00
Andrew Waterman
bccbf3b3de Merge pull request #2093 from chihminchao/ext-zibi 
new extension : zibi
 2025-10-01 15:06:45 -07:00
Chih-Min Chao
7b060d0d86 disasm: show the acquire and release attribute to amo instructions 
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
 2025-09-30 22:59:56 -07:00
Chih-Min Chao
e2e02098a4 ext: add zibi 
It implement v0.6 version

reference
    https://github.com/riscv/zibi/releases/download/v0.6/zibi.pdf
    https://riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
 2025-09-30 22:57:32 -07:00
Andrew Waterman
3232ce1b76 Implement Zvflqdot8f 2025-09-30 19:13:53 -07:00
Andrew Waterman
e3dc14a878 Implement Zvfbqdot8f 2025-09-30 19:13:10 -07:00
Andrew Waterman
1d56b556b5 Relax VLEN/ELEN checking 
We should allow ISA strings like rv64gc_zve32f.  Per the spec, the
various Zve extensions imply a minimum VLEN, so rv64gc_zve32f
is unambiguously equivalent to rv64gc_zve32f_zvl32b. Similarly,
rv64gc_zve64x, rv64gc_zve64x_zvl64b, and rv64gc_zve64x_zvl32b are
all unambiguously equivalent.
 2025-09-04 14:47:37 -07:00
Andrew Waterman
faeae4eada VLEN is unitless 2025-09-04 14:42:11 -07:00
Andrew Waterman
acac77d59d No tabs 2025-09-04 14:36:06 -07:00
Andrew Waterman
19409bdfac Merge pull request #2065 from riscv-software-src/ldot 
Add Zvldot extension support
 2025-09-04 00:54:44 -07:00
Andrew Waterman
dcef3e5881 Merge pull request #2054 from nadime15/update_vlen_elen 
Add VLEN >= ELEN validation check
 2025-09-03 19:49:49 -07:00
Andrew Waterman
717a6e275c Add Zvldot extension support 2025-09-03 19:49:23 -07:00
Nadime Barhoumi
dcb5f0c784 Remove redundant checks in Zfbfmin and Zvfbfmin validation 2025-08-28 10:22:02 -04:00
Nadime Barhoumi
715c1597ab Fix BFloat16 vector extension dependencies 
* Enable EXT_INTERNAL_ZFH_MOVE when either Zfbfmin or Zfhmin is enabled
* Change Zvfbfmin to require Zve32f instead of V extension.
* Add proper dependency chain for Zvfbfwma requiring both Zvfbfmin and Zfbfmin.
 2025-08-28 10:22:02 -04:00
Nado15
23ad840e4d Add VLEN < ELEN validation check 2025-08-08 00:07:54 -04:00
Andrew Waterman
dd4d3fbca9 Implement Zvbdot draft 2025-08-05 23:57:07 -07:00
Hao
9950cb3d59 fix: check ext_str size when ext = zve* 
`zve*`  = "zve{32, 64}{x, f, d}", size of `zve*` must be 6.

Signed-off-by: Hao <58808837+ha0lyu@users.noreply.github.com>
 2025-08-03 13:46:01 +08:00
Andrew Waterman
cce834e437 Support Ziccid extension 2025-06-12 17:05:09 -07:00
Andrew Waterman
b6a061b683 Support Ziccif extension 2025-06-12 16:28:35 -07:00
YenHaoChen
d4abc9a71b AIA: Enable Smcsrind/Sscsrind if supporting Smaia/Ssaia 
Smaia/Ssaia allocates indirect CSRs 0x30~0x3f for major interrupt
priorities and 0x70~0xff for external interrupts (only with an IMSIC).
 2025-05-14 00:16:15 -07:00
YenHaoChen
8050278445 AIA: Add isa=..._smaia_ssaia_... option 2025-05-13 20:50:10 -07:00
Muhammad Moiz Hussain
4764d3c029 Implement Ssccfg & Smcdeleg for spike 
Signed-off-by: muhammad.moiz.hussain@semidynamics.com
 2025-04-23 12:01:45 +02:00
Andrew Waterman
5ef9a61f5f Merge pull request #1942 from trdthg/svade 
Add Svadu/Svade Support
 2025-04-17 01:32:28 -07:00
Mingzhu Yan
4d3920b262 Add Svade extension Support 
Spike always supports the Svade extension, this is required by the RVA and RVB profiles
 2025-04-17 15:49:35 +08:00
Andrew Waterman
b645cc0fba Explicitly annotate fallthrough cases (-Wextra) 2025-04-16 16:03:13 -07:00
Andrew Waterman
8ccde08b27 Remove unused functions (-Werror) 2025-04-16 13:32:51 -07:00
Mahmoud Abumandour
cfa593d0ea isa_parser: don't append one char at a time in strtolower 
This avoids potential re-alloations as it allocates the result string
upfront.
 2025-04-15 21:42:12 -07:00
Andrew Waterman
5ed426bbf4 Add Zvqdotq extension 
Not yet frozen, but in a pretty stable state.

See https://github.com/riscv/riscv-dot-product
 2025-02-14 17:49:54 -08:00
Andrew Waterman
1e589aa502 Support strict disassembly in disassembler_t 2024-12-17 23:06:07 -08:00
Christian Herber
ff771919ec Updated load/store pair for RV32 to v0.10 
- renamed Zcmlsd to Zclsd
- bumped version number
 2024-10-04 12:42:16 +02:00
Andrew Waterman
9a641bb03e Validate Zvl ISA string correctly 
See #1810 for explanation of how this can go wrong.

Resolves #1810
 2024-09-20 04:39:18 -07:00
Andrew Waterman
19fdd76e05 Merge pull request #1811 from riscv-software-src/fix-1810 
Validate Zvl ISA string correctly
 2024-09-20 04:18:17 -07:00
Andrew Waterman
6b74bd669d Validate Zvl ISA string correctly 
See #1810 for explanation of how this can go wrong.

Resolves #1810
 2024-09-20 04:06:38 -07:00
Jerry Zhao
b47080fea4 Remove --with-priv compile flag 2024-09-14 01:17:31 -07:00
YenHaoChen
6a1a5db16b vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector widening floating-point fused multiply-add instructions 2024-09-03 08:57:13 +08:00
YenHaoChen
b47d0baab3 vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single-width floating-point fused multiply-add instructions 2024-09-03 08:57:13 +08:00
YenHaoChen
7f38a503d0 vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector widening integer multiply-add instructions 2024-09-03 08:57:06 +08:00
YenHaoChen
ff62109211 vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single-width integer multiply-add instructions 2024-09-03 08:56:58 +08:00
Andrew Waterman
f09b02460e Merge pull request #1722 from ved-rivos/smdbltrp 
Add Smdbltrp
 2024-08-18 18:43:57 -05:00
Jerry Zhao
9031c7b651 Fix ordering of B single-letter extension 
The canonical order is IMAFDQLCBKJTPVH

Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>
 2024-08-11 16:42:36 -07:00
Ved Shanbhogue
c302e8bd16 Add Smdbltrp 2024-08-07 09:27:05 -05:00
YenHaoChen
370f741a97 pointer masking: Support _ssnpm to --isa 2024-07-06 03:30:41 +08:00
YenHaoChen
eea20ae6a2 pointer masking: Support _smnpm to --isa 2024-07-06 03:30:41 +08:00
YenHaoChen
436b684ff5 pointer masking: Support _smmpm to --isa 2024-07-06 03:29:30 +08:00
Ved Shanbhogue
0797c21001 Add Ssdbltrp 2024-07-06 08:40:08 -05:00
Andrew Waterman
6854a911fd Expand default disassembly ISA 2024-06-26 18:10:27 -07:00
Andrew Waterman
389851ce15 Add disassembly for Zfa extension 2024-06-26 18:10:13 -07:00
Rafael Sene
ef7416ce1d Fix: Add missing <stdexcept> header for std::logic_error 
- Included <stdexcept> in isa_parser.cc to resolve compilation error due to missing type 'std::logic_error'.

Signed-off-by: Rafael Sene <rafael@riscv.org>
 2024-06-22 11:26:41 -03:00
Jerry Zhao
67e205c289 Restrict spike to vlen <= 4096 2024-06-21 10:29:20 -07:00
Jerry Zhao
457ea8c0cd Relax zvfh/zvfhmin dependency on V, they only actually depend on Zve 2024-06-21 10:29:19 -07:00