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2874 Commits

Author SHA1 Message Date
Andrew Waterman
38eec3f323 Merge pull request #2097 from riscv-software-src/fix-werror 
Actually use -Werror in CI again
 2025-10-01 23:41:39 -07:00
Andrew Waterman
e69c5376a5 Suppress warning for unused write() result 2025-10-01 16:20:20 -07:00
Andrew Waterman
9ea67d0ca8 Add UNUSED to suppress warning 2025-10-01 16:11:49 -07:00
Andrew Waterman
eb90f5aa75 Add default destructor to suppress warning 2025-10-01 16:11:49 -07:00
Andrew Waterman
837fcf7c15 Avoid VLAs 2025-10-01 16:11:49 -07:00
Andrew Waterman
bccbf3b3de Merge pull request #2093 from chihminchao/ext-zibi 
new extension : zibi
 2025-10-01 15:06:45 -07:00
Andrew Waterman
aee4555eea Merge pull request #2092 from riscv-software-src/zvfqbdot8f 
Implement Zvfqbdot8f and Zvfqldot8f
 2025-10-01 00:32:58 -07:00
Chih-Min Chao
e2e02098a4 ext: add zibi 
It implement v0.6 version

reference
    https://github.com/riscv/zibi/releases/download/v0.6/zibi.pdf
    https://riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
 2025-09-30 22:57:32 -07:00
Chih-Min Chao
4c6be8305c update encoding.h 
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
 2025-09-30 22:45:10 -07:00
Andrew Waterman
3232ce1b76 Implement Zvflqdot8f 2025-09-30 19:13:53 -07:00
Andrew Waterman
e3dc14a878 Implement Zvfbqdot8f 2025-09-30 19:13:10 -07:00
Andrew Waterman
a07e44071f Use bulk normalization algorithm for Zvfqbdot8f 2025-09-30 19:09:41 -07:00
Andrew Waterman
3b066d68fe Merge pull request #2089 from chihminchao/fix-mseccfg-rv32 
csr: fix mseccfg for rv32
 2025-09-30 14:31:03 -07:00
Chih-Min Chao
180c10fe42 csr: fix mseccfg for rv32 
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
 2025-09-30 00:45:24 -07:00
Ved Shanbhogue
cfd4930cb6 PTE store in s2xlate should use the trap_type instead of type 2025-09-25 19:13:14 -05:00
Andrew Waterman
18bcac3d94 Prevent div-by-0 when executing Zvbdot instructions with VLEN=0 
Fixes #2076
 2025-09-09 03:45:14 -07:00
Andrew Waterman
545712a6f7 Merge pull request #2074 from riscv-software-src/fix-2073 
Allow DEBUG_START to be nonzero again
 2025-09-08 16:35:36 -07:00
Andrew Waterman
e80b890ebf Suppress -Wtype-limits warning 2025-09-08 16:14:16 -07:00
Ved Shanbhogue
743732c3e6 Clear SDT in the temporary state variable 2025-09-07 16:51:44 -05:00
Andrew Waterman
717a6e275c Add Zvldot extension support 2025-09-03 19:49:23 -07:00
Andrew Waterman
cfc472e83b Use f32_add_bulknorm_odd for vfwbdot 2025-09-03 18:48:08 -07:00
Andrew Waterman
cf7d57ef74 Add f32_add_bulknorm_odd routine 
Used by Zvldot/Zvbdot
 2025-09-03 18:33:37 -07:00
Binno
faeecd8d72 Revert "Don't shift enabled bits of interrupt in vstopi csrs" 
This reverts commit e515a8fbcd.
 2025-08-27 22:54:17 -07:00
Binno
e515a8fbcd Don't shift enabled bits of interrupt in vstopi csrs 
Signed-off-by: Binno <binno.shen@sifive.com>
 2025-08-10 19:43:23 -07:00
Andrew Waterman
d0c345184f Support FLI.H for Zfa && Zvfh && !Zfh 
Resolves #2052
 2025-08-06 23:09:33 -07:00
Andrew Waterman
d951d9bc6a Fix regression introduced by #2050 
Don't assert SEW=8 for fp16 <> int8 conversions.
 2025-08-06 16:05:09 -07:00
Andrew Waterman
5da583ee34 Merge pull request #2050 from riscv-software-src/vfp-refactor 
Factor out common vector FP prologue
 2025-08-06 15:01:46 -07:00
Andrew Waterman
4e4d9f99ee Factor out rounding-mode validation 2025-08-06 14:40:50 -07:00
Andrew Waterman
3c0db13b52 Factor out common vector FP prologue 2025-08-06 14:33:28 -07:00
Andrew Waterman
d3b3fcba82 Use class member initialization in vector unit 2025-08-06 00:00:29 -07:00
Andrew Waterman
c04d2381d1 Remove dead code in vector unit 2025-08-05 23:59:37 -07:00
Andrew Waterman
dd4d3fbca9 Implement Zvbdot draft 2025-08-05 23:57:07 -07:00
hdinc
d62d3075a2 ns16550.cc : fix handling clear rx/tx FIFO requests. 
Signed-off-by: hdinc <macellan091@gmail.com>
 2025-08-03 15:08:39 +03:00
Knute Lingaard
4ecd2e7e79 Merge branch 'master' into klingaard/issue_2038_quad_logging_store_issue 2025-07-31 15:52:46 -05:00
Knute Lingaard
09e4d6d089 Fixed issues with logging 2025-07-31 08:42:15 -05:00
Muhammad Moiz Hussain
5063dcb8ea Sireg is not in the sireg_csrs[] list, so needs to be checked outside of the switch-case 2025-07-31 12:06:30 +02:00
Andrew Waterman
8da8b6a34d Don't include built-in devices in mmio_device_map 
Only use mmio_device_map for plugin devices.

This fixes a collision caused by multiple static initializers if Spike
depends on a library that depends on libriscv.so.
 2025-07-30 13:46:04 -07:00
Andrew Waterman
c61e4bccce Remove brittle reliance on ordering of factory table 2025-07-30 13:07:06 -07:00
Andrew Waterman
483e01d486 Merge pull request #2037 from riscv-software-src/2036-redux 
Only support 56-bit PMP and ATP addresses
 2025-07-29 14:48:58 -07:00
Andrew Waterman
352597c4cf Remove MAX_PADDR_BITS 
It isn't used anymore.
 2025-07-28 20:10:34 -07:00
Andrew Waterman
a89875689e Only support 56-bit PMP addresses 
As mandated by the ISA spec.
 2025-07-28 20:09:33 -07:00
Andrew Waterman
72e8cad123 Implement processor_t::paddr_bits correctly 
It wasn't being called anywhere, so the 50- vs. 56-bit discrepancy
never manifested.
 2025-07-28 20:08:32 -07:00
Andrew Waterman
94beb3c026 Remove physical address checks in sim_t 
Processors are responsible for validating physical addresses; the bus
is only responsible for making some device lives at a given address.
 2025-07-28 20:08:02 -07:00
Ian Huang
b6f4d246bc AIA: vstopi should only be used for AIA-extended interrupts 
VSEIP/VSTIP/VSSIP should come in through the non-SSAIA path.
vstopi will be used to throw VTI and IID > 13 interrupts.
 2025-07-15 14:50:18 -07:00
Andrew Waterman
965547260a Merge pull request #2025 from mslijepc/mslijepc_20250702_additional-files-riscvmkin 
added jtag_dtm and remote_bitbang to riscv_install_hdrs
 2025-07-03 13:37:02 -07:00
mslijepc
d2cf8b0419 added jtag_dtm and remote_bitbang to riscv_install_hdrs 2025-07-02 17:40:39 +02:00
Farid Khaydari
9b2a1d6c81 Add DCSR.MPRVEN support 
Adds DCSR.MPRVEN bit support, as specified in RISC-V External Debug Support Version 1.0.0-rc4
(https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc4, see 4.9.1 Debug Control and Status).

This bit allows to enable hardware virtual address translation when memory access
is initiated by the debugger (see 4.1 Debug Mode, clause 2).

This change:
* Increases debug specification coverage, allows more detailed testing of external debuggers with Spike.
* Decreases the number of required abstract commands to read virtual memory thus improving the user experience.

Commit's changes:
* Added MPRVEN field to DCSR register
* Updated debug_rom.S to turn off MPRVEN on memory access

To avoid unwanted address translation while debug_rom.S executed
DCSR.MPRVEN bit has to be cleared before and restored after access.

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
 2025-07-01 18:25:11 +03:00
Andrew Waterman
ba54a6015f Merge pull request #2022 from aap-sc/aap-sc/another_unused_variable_warning 
remove unused EGS constant from vsm4r_vs handler
 2025-06-28 12:11:46 -07:00
Parshintsev Anatoly
7f8aa45514 remove unused EGS constant from vsm4r_vs handler 
The macro require_vsm4_constraints defines EGS once again (shadowing
the definition of this constant, since it introduces a new scope). This
renders the original definition as "unused", causing warning during
compilation.
 2025-06-28 10:06:59 +03:00
Parshintsev Anatoly
380efd9b80 fixed warnings about unused parameter when csrs.h file is included 2025-06-28 01:22:15 +03:00