3754 Commits

Author SHA1 Message Date
Andrew Waterman
7b6911f56f
Add note about tvec/jvt register layout/alignment (#1988)
Supersedes #1987
riscv-isa-release-7b6911f-2025-04-25 riscv-isa-release-7b6911f-2025-04-30
2025-04-25 15:58:54 -07:00
Andrew Waterman
a7713b9f1e
Clarify <nf> in asm syntax equals NFIELDS (#1986)
Resolves #1983
riscv-isa-release-a7713b9-2025-04-24
2025-04-24 13:31:16 -07:00
Bill Traynor
5308687fe8
Merge pull request #1980 from jaimiejellema/main
Typographical fixes to xperm and packw instruction listing
riscv-isa-release-5308687-2025-04-22
2025-04-22 09:01:04 -04:00
Jaimie Jellema
a04916e2b9 Typographical fixes to xperm and packw instruction listing 2025-04-21 04:08:53 +02:00
Brian Grayson (MIPS)
e5078e55ea
Three minor documentation tweaks (#1974)
* Clarified aspects of Zce, MISA.C, and the D extension

* Clarified that invoking *ret instructions in a lesser privilege mode results in an illegal-instruction exception

* Reworded sentence about load/store-multiple instructions

* Removed excess D reference, since D implies F

* Reworded to use __x__ forms
riscv-isa-release-e5078e5-2025-04-15
2025-04-15 00:22:11 +00:00
Prashanth Mundkur
567502bebd
Fix a broken extension reference. (#1968)
'zbkbc' is likely a typo since no such extension exists; from the
context, it probably means 'zbkb'.
riscv-isa-release-567502b-2025-04-10
2025-04-10 16:20:32 -07:00
Radim Krčmář
505d955607
hypervisor: add HUPMM to hstatus (#1967)
* hypervisor: translate hstatus to wavedrom

The bytefield is hardly maintainable.

Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>

* hypervisor: add HUPMM to hstatus

HUPMM was forgotten when the pointer masking extension was added.

Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>

---------

Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>
riscv-isa-release-505d955-2025-04-10
2025-04-10 20:38:14 +00:00
Andrew Waterman
d83114cc46
Clarify that vaadd intermediate results aren't truncated (#1960) riscv-isa-release-d83114c-2025-04-10 2025-04-09 17:20:31 -07:00
Ved Shanbhogue
0e940b0f54
Add missing SSE bit in senvcfg for RV32 (#1965) riscv-isa-release-0e940b0-2025-04-09 2025-04-09 16:43:54 -07:00
Craig Topper
869612154a
Remove [5:4] after spimm in cm.push/pop wavedrom and assembly syntax explanation. (#1953)
The text refers to spimm as "the number of additional 16-byte address increments allocated for the stack frame."
and "The total stack adjustment represents the total size of the stack frame, which is stack_adj_base added
to spimm scaled by 16"

The "Example RV32I PUSH/POP sequences" show spimm with values of 0-3.

Based on those sections, I think spimm is a 2-bit value rather than a 6-bit value.
riscv-isa-release-8696121-2025-04-04
2025-04-04 14:33:36 -07:00
Andrew Waterman
600b757e54
Make priv preface consistent with unpriv preface (#1947) riscv-isa-release-600b757-2025-04-02 2025-04-02 00:05:45 -07:00
Andrew Waterman
14c7ae3193
Merge pull request #1946 from riscv/ratified-only
Remove VLIW and longer instruction encoding proposals
riscv-isa-release-14c7ae3-2025-04-02
2025-04-01 19:36:54 -07:00
Andrew Waterman
4f05ffef49 Remove proposal for longer instruction encodings
This is pursuant to making the manual contain only ratified content.
2025-04-01 18:02:36 -07:00
Andrew Waterman
9092013a8a Remove VLIW encoding proposal
This is pursuant to making the manual contain only ratified content.
2025-04-01 18:02:05 -07:00
Andrew Waterman
b143ec86db
Rename mstateen0.P1P14 to mstateen0.SRMCFG (#1945)
Since it was ratified as part of Ssqosid, there are actually no priv-1.14
changes in flight, so revert the version number to 1.13.
riscv-isa-release-b143ec8-2025-04-02
2025-04-01 17:55:44 -07:00
Andrew Waterman
372edf9994
Clarify description of constrained LR/SC loops for Zca++ (#1939)
This PR fixes an editing error in which "C" should have been changed to
"Zca" when the various Zc extensions were incorporated.  It also clarifies
that any compressed instruction, not just those in Zca, that map to one of the
permitted "I" instructions can be used in a constrained LR/SC loop.  This
was always the case, but it was stated obliquely.

Resolves #1938
riscv-isa-release-372edf9-2025-04-01
2025-04-01 16:44:32 -07:00
Andrew Waterman
acebdff1fd
Remove P extension placeholder chapter (#1943)
This is pursuant to making the manual contain only ratified content.

Note, this action does not connote any deprecation of the forthcoming Zp
extensions for packed SIMD.  They, like all in-progress extensions, will
be incorporated into the manual upon ratification.
riscv-isa-release-acebdff-2025-04-01
2025-04-01 16:16:19 -07:00
Andrew Waterman
d3f3eaaa23
Merge pull request #1942 from riscv/remove-rv128
Remove RV128 content from ISA spec
2025-04-01 16:16:07 -07:00
Andrew Waterman
546af350c4 Remove RV128 chapter 2025-04-01 15:00:13 -07:00
Andrew Waterman
47f167bd03 Remove RV128 references from Zacas chapter 2025-04-01 15:00:13 -07:00
Andrew Waterman
b7c8a7f23b Remove RV128 references from RVWMO chapter 2025-04-01 15:00:13 -07:00
Andrew Waterman
1e3eb3d4a4 Remove RV128 references from RVG instruction listings 2025-04-01 15:00:13 -07:00
Andrew Waterman
d211e71abc Remove RV128 references from Q chapter 2025-04-01 15:00:13 -07:00
Andrew Waterman
415d54097c Remove RV128 references from Naming chapter 2025-04-01 15:00:12 -07:00
Andrew Waterman
cf33dccb0f Remove RV128 references from Intro 2025-04-01 15:00:12 -07:00
Andrew Waterman
3b96bbeb08 Remove RV128 references from Extending RISC-V chapter 2025-04-01 15:00:12 -07:00
Andrew Waterman
97dcf0d655 Remove RV128 references from Machine chapter 2025-04-01 15:00:12 -07:00
Andrew Waterman
2948fbc990 Remove RV128 references from C instruction listing 2025-04-01 15:00:12 -07:00
Andrew Waterman
afba55c0bb Remove RV128 references from C chapter 2025-04-01 15:00:12 -07:00
Andrew Waterman
d1fe66d3ef Remove RV128 references from C opcode table 2025-04-01 15:00:12 -07:00
Andrew Waterman
6eaad602b4 Remove RV128 references from B chapter 2025-04-01 15:00:12 -07:00
Andrew Waterman
cff609edf3
Fix minor transliteration bugs in RVC instruction listing (#1941) riscv-isa-release-cff609e-2025-04-01 2025-04-01 13:51:12 -07:00
Alexander Richardson
7081c0ba96
Add a flag to allow faster (but unreliable) incremental builds (#1937)
Setting UNRELIABLE_BUT_FASTER_INCREMENTAL_BUILDS=1 on the make command line
will avoid wiping the entire build directory before builds. Since each
output file uses a different build directory there should be no
need to wipe the whole build directory. The Makefile already triggers a
rebuild if any file under the source directory is modified so this should
be safe.
This significantly speeds up the build for me since we no longer regenerate
all the diagrams for each build. For the unprivileged manual the build time
goes from about 4:30 to 3:40.

However, it has been shown that non-clean builds don't always produce the
same output PDF, so this is gated by an opt-in flag.
riscv-isa-release-7081c0b-2025-03-31
2025-03-31 13:03:36 -07:00
Alexander Richardson
129a2f9bc8
Remove unused mseccfg.edn bytefield (#1934)
It uses wavedrom since https://github.com/riscv/riscv-isa-manual/pull/1380
riscv-isa-release-129a2f9-2025-03-27
2025-03-27 15:18:58 -07:00
Bill Traynor
f122839269
Merge pull request #1932 from mmhus/mmhus/fix-smcntrpmf-heading
[#1933] Fixed Smcntrpmf heading not showing up in riscv-privileged.pdf
riscv-isa-release-f122839-2025-03-27
2025-03-27 11:56:15 -04:00
Muhammad Moiz Hussain
53876ede05 Fixed Smcntrpmf heading not showing up in riscv-privileged.pdf
Fixes: 1929d45a059979c55b070fba414d97d530a44c99
Author: mmoizhussain

 On branch mmhus/fix-smcntrpmf-heading
 Changes to be committed:
	modified:   src/smcntrpmf.adoc
2025-03-27 14:44:25 +01:00
Andrew Waterman
1929d45a05
Clarify exception behavior of segment fault-only-first loads (#1930) riscv-isa-release-1929d45-2025-03-26 2025-03-26 15:57:20 -07:00
Mark Zhuang
482805da38
Remove unused var count (#1926) riscv-isa-release-482805d-2025-03-25 2025-03-25 21:36:30 +00:00
Bill Traynor
bb8b9127f8
Merge pull request #1921 from pmundkur/fixes
Fix a step reference for Sv32 address translation.
riscv-isa-release-bb8b912-2025-03-21
2025-03-21 10:36:17 -04:00
Prashanth Mundkur
1a80d5ddf9 Fix a step reference for Sv32 address translation.
This got out of sync due to steps added in #1742.

Also fix an unrelated typo.
2025-03-21 09:13:55 -05:00
Bill Traynor
5c2f66f060
Merge pull request #1918 from arichardson/pre-commit-ci
Add pre-commit hooks to CI
riscv-isa-release-5c2f66f-2025-03-20
2025-03-20 16:06:38 -04:00
Alex Richardson
94f8697ca4 Add the pre-commit hooks from the docs-spec-template repository
This will ensure consistent line endings and valid yaml/json.
Can be enabled using `pre-commit install`.
2025-03-20 11:33:23 -07:00
Alex Richardson
fa4f57662d Fix trailing whitespace and line endings
Using `pre-commit run --all-files`
2025-03-20 11:33:23 -07:00
Alex Richardson
cea2e60db7 Run YAML formatter
Using `pre-commit run --all-files`
2025-03-20 08:56:01 -07:00
Bill Traynor
ee6fbb5288
Merge pull request #1917 from arichardson/github-pages
Deploy a snapshot of the specification to GitHub pages
riscv-isa-release-ee6fbb5-2025-03-20
2025-03-20 08:53:40 -04:00
Alexander Richardson
2336fdc64f
ci: Avoid printing "docker: not found" error messages (#1916)
This could be fixed by adding `2>&1` to the `docker info` command, but
it seems cleaner to correctly infer the value of SKIP_DOCKER and avoid
entering the whole `ifneq ($(SKIP_DOCKER),true)` block.
riscv-isa-release-2336fdc-2025-03-19
2025-03-19 13:34:25 -07:00
Alex Richardson
688dc4c213 Add a link to the HTML snapshot of the latest commit to README.md 2025-03-19 11:23:51 -07:00
Alex Richardson
56ee3e045d Deploy a snapshot of the specification to GitHub pages
This makes it easier to view the latest snapshot without having to download a
PDF from the releases page. The snapshots are deployed at the following URLs:
- [Unprivileged spec](https://riscv.github.io/riscv-isa-manual/snapshot/unprivileged/).
- [Privileged spec](https://riscv.github.io/riscv-isa-manual/snapshot/privileged/).

The HTML is deployed to a snapshot/ subdirectory to make it possible to also
deploy versioned releases in the future.
2025-03-19 11:17:26 -07:00
Prashanth Mundkur
0a36d5f55a
Fix a typo and edit for clarity. (#1914)
. Conversions narrowing to BF16 end up at BF16, not the target
  precision (which is the origin of the conversion).

. Capitalize an 'i' at sentence start.

. Remove repetition of C bit in *stateen0 not being custom state.

. Remove a misplaced 'of'.
riscv-isa-release-0a36d5f-2025-03-18
2025-03-18 21:31:15 +00:00
Andrew Waterman
fe7bd31bb9
Replace "Sv39" with "Sv39 extension" where appropriate (#1913) riscv-isa-release-fe7bd31-2025-03-18 2025-03-17 18:30:57 -07:00