riscv/riscv-opcodes
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confprec
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Quan Nguyen 612076a5c7 Add vsetprec instruction
2013-11-29 20:24:44 -08:00
.gitignore
add gitignore
2013-10-18 22:30:10 -07:00
inst.chisel
fix slli/slliw encoding bug
2013-11-21 14:40:33 -08:00
instr-table.tex
add missing imm for stores
2013-11-22 14:06:49 -08:00
Makefile
Merge branch 'master' into confprec
2013-11-24 22:04:23 -08:00
opcodes
Merge branch 'master' into confprec
2013-11-24 22:04:23 -08:00
opcodes-custom
Update ISA encoding
2013-09-21 06:43:00 -07:00
opcodes-hwacha
Add vsetprec instruction
2013-11-29 20:24:44 -08:00
opcodes-hwacha-pseudo
revamp hwacha-v3 opcodes
2013-10-10 12:05:24 -07:00
opcodes-hwacha-ut
Move half-precision opcodes to opcodes-hwacha-ut
2013-10-27 21:56:24 -07:00
opcodes-rvc
Factor out Hwacha/RVC and rename MFTX/MXTF to FMV
2013-07-26 17:46:42 -07:00
parse-opcodes
add missing imm for stores
2013-11-22 14:06:49 -08:00
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BSD-3-Clause 1.8 MiB
Languages
Python 80.5%
C 18.2%
Makefile 1.3%