Default Branch

56546ec382 · don't depend on matplotlib unless -svg is passed on command line (#376) · Updated 2025-10-10 08:32:14 +08:00

Branches

2de45514d2 · Refactored and modularized C Artifact Generation · Updated 2024-11-27 23:39:24 +08:00

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db3d5f1368 · Pre commit fixes · Updated 2024-11-21 00:36:17 +08:00

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36f37737b8 · Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv-opcodes into incoresemi-migration-to-new-format · Updated 2022-05-03 05:20:35 +08:00

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Included

71cd23ab5d · Add RNMI CSRs and instruction · Updated 2022-02-22 14:27:04 +08:00

371
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2d4df20c01 · Add wfmi instruction · Updated 2021-06-08 04:15:43 +08:00

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76bc825357 · Remove subu.w · Updated 2020-11-14 09:15:44 +08:00

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Included
zfh

af61a81535 · Add tentative RV32Zfh encoding · Updated 2020-03-26 03:28:35 +08:00

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2c8bd05887 · Update encoding of vadc and friends · Updated 2019-11-05 07:50:21 +08:00

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rvv

12201427cf · Fix config imms · Updated 2019-02-02 02:39:48 +08:00

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v

8f474fca14 · CSRRx is called Zicsr · Updated 2018-11-07 11:16:54 +08:00

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388bb93d4e · Update the debug CSR definitions for the proposed 0.13 debug spec · Updated 2017-03-08 08:36:54 +08:00

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6dbc75bb78 · WIP: auto-generate llvm encoding file · Updated 2016-07-13 20:34:43 +08:00

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mvp

79e317971c · Add vf[ls]seg(|st)h and friends · Updated 2014-04-29 15:36:49 +08:00

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612076a5c7 · Add vsetprec instruction · Updated 2013-11-30 12:24:44 +08:00

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Included