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See https://github.com/riscv/riscv-v-spec/pull/317
riscv-opcodes
This repo enumerates standard RISC-V instruction opcodes and control and status registers. It also contains a script to convert them into several formats (C, Scala, LaTeX).
This repo is not meant to stand alone; it is a subcomponent of riscv-tools and assumes that it is part of that directory structure.
Description
Languages
Python
80.5%
C
18.2%
Makefile
1.3%