Add Xilinx Zynq BSP support

This commit is contained in:
Sebastian Huber
2015-01-20 11:04:39 +01:00
parent dae9f66600
commit 5071600b21
3 changed files with 37 additions and 0 deletions

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@@ -56,4 +56,36 @@ RTEMS_BSD_DEFINE_NEXUS_DEVICE(smc, 0, RTEMS_ARRAY_SIZE(smc0_res),
RTEMS_BSD_DEFINE_NEXUS_DEVICE(fec, 0, 0, NULL);
#elif defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
#include <bsp/irq.h>
static const rtems_bsd_device_resource zy7_slcr0_res[] = {
{
.type = RTEMS_BSD_RES_MEMORY,
.start_request = 0,
.start_actual = 0xf8000000
}
};
RTEMS_BSD_DEFINE_NEXUS_DEVICE(zy7_slcr, 0, RTEMS_ARRAY_SIZE(zy7_slcr0_res),
&zy7_slcr0_res[0]);
static const rtems_bsd_device_resource cgem0_res[] = {
{
.type = RTEMS_BSD_RES_MEMORY,
.start_request = 0,
.start_actual = 0xe000b000
}, {
.type = RTEMS_BSD_RES_IRQ,
.start_request = 0,
.start_actual = ZYNQ_IRQ_ETHERNET_0
}
};
RTEMS_BSD_DEFINE_NEXUS_DEVICE(cgem, 0, RTEMS_ARRAY_SIZE(cgem0_res),
&cgem0_res[0]);
SYSINIT_DRIVER_REFERENCE(e1000phy, miibus);
#endif

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@@ -27,6 +27,9 @@
#if defined(LIBBSP_ARM_LPC24XX_BSP_H)
/* No cache */
#elif defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
/* With cache, no coherency support in hardware */
#define CPU_DATA_CACHE_ALIGNMENT 32
#elif defined(LIBBSP_ARM_LPC32XX_BSP_H)
/* With cache, no coherency support in hardware */
#include <libcpu/cache.h>

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@@ -36,6 +36,8 @@
#if defined(LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H)
#define NET_CFG_INTERFACE_0 "smc0"
#elif defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
#define NET_CFG_INTERFACE_0 "cgem0"
#elif defined(__GENMCF548X_BSP_H)
#define NET_CFG_INTERFACE_0 "fec0"
#else