Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
The following files are now provided by Newlib:
* arpa/inet.h
* net/if.h
* netinet/in.h
* netinet/tcp.h
* sys/socket.h
* sys/uio.h
* sys/un.h
The <sys/param.h> and <sys/cpuset.h> are now compatible enough to be
used directly.
Update #2833.
