Kinsey Moore cf8fa08015 rtemsbsd/arasan_sdhci: Remove redundant clock cap
The BSD SD subsystem enforces a 50MHz clock cap for devices which don't
report their own maximum clock speed. This setting is unnecessary for
the Zynq 7000 version of this IP and restricts the Zynq Ultrascale+
MPSoC version of this IP without need since it reports its maximum speed
as 200MHz.
2022-10-21 15:10:43 -05:00
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2021-08-28 10:25:46 +10:00
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