The BSD SD subsystem enforces a 50MHz clock cap for devices which don't
report their own maximum clock speed. This setting is unnecessary for
the Zynq 7000 version of this IP and restricts the Zynq Ultrascale+
MPSoC version of this IP without need since it reports its maximum speed
as 200MHz.
The initial version of this driver was masking the capabilities register
to hide 8 bit bus capability. This is not necessary since these devices
report that capability correctly and the masking affects performance
negatively on ZynqMP boards where the 8 bit bus is supported. This also
removes two quirks that were made necessary by the capabilities masking.
Probing a SDIO/SDHCI interface that has been disabled by system init via
holding it in reset can cause a CPU hang. This prevents probing of
devices that have been disabled in such a manner on ZynqMP systems.
The standard FreeBSD MII support causes severe problems on the LPC3200
chip family. If an Ethernet module register is accessed while there is
no clock from the PHY, the chip completely locks up and only an external
watchdog can recover from this state. The legacy driver had a custom
PHY management code which helped to avoid such issues. The if_lpe.c
driver is no longer maintained by FreeBSD.
Under unknown conditions the receive path ended up in a frozen state.
In this state, the DMA and driver descriptor head were equal and all
receive descriptors had the used bit set. So, the DMA was unable to
store received frames. However, the receive daemon was never woken up
to refill the receive buffers. It seems that the RXUBR interrupt can be
used to recover from this state.
Update #4652.
Do not use the interface mutex in the receive loop. Avoid multiple
reads of DMA descriptor words. Use a compile-time constant for the
receive DMA descriptor count to simplify calculations.
Update #4652.
Use the transmit interface handler to avoid a transmit task/interrupt.
Use a compile-time constant for the transmit DMA descriptor count to
simplify calculations.
Update #4652.
The pppstart expected that a driver write would somehow magically
process all data passed to the write function. Because ppp disables all
buffering that originally has been in termios, that assumption is not
true for all but polled drivers.
With this patch, the pppstart now gets and processes the feedback that
is returned from the driver via rtems_termios_dequeue_characters.
Fixes#4493
Possible data sources for SD driver:
- mmc_sd_switch():
- length: 64 byte;
- buffer on stack
- mmc_test_bus_width():
- length: 4 or 8 byte
- buffer in program memory or on stack
- mmc_app_send_scr():
- length: 8 byte
- buffer from device ivar structure
- mmc_app_sd_status():
- length: 64 byte
- buffer from device ivar structure
- mmc_send_ext_csd():
- length: MMC_EXTCSD_SIZE = 512
- buffer from device ivar structure
- rtems_bsd_mmcsd_disk_read_write():
- length: depends on read
- buffer from rtems_blkdev buffer -> already aligned
- mmcsd_ioctl_cmd():
- length: depends on call
- buffer malloced, not aligned -> patched in RTEMS
So the problematic buffers are only the ones up to 512 bytes. Copy these data
into a buffer to avoid that problem.
Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
